1. Caltech intermediate form code is a A. low-level graphic language B. low-level textual language C. high-level graphic language D. high-level textual language 2. CIF generates code that is A. high-level language B. assembly level language C. machine-readable language D. very high-level language 3. CIF code is compatible with A. low system geometry B. …
1. In which design all circuitry and all interconnections are designed? A. full custom design B. semi-custom design C. gate array design D. transistor design 2. Which design contains only the interconnections designed? A. full custom design B. semi-custom design C. gate array design D. transistor design 3. In which method regularity is …
VLSI Design Style MCQ Quiz – Objective Question with Answer for VLSI Design Style Read More »
1. The Zp.u./Zp.d. ratio for the nMOS inverter is A. 4:1 B. 3:1 C. 1:4 D. 1:3 2. The impedance ratio for pseudo-nMOS is A. 4:1 B. 3:1 C. 1:4 D. 1:3 3. What is the value of peripheral capacitance for 5-micron technology? A. 4 × 10(-4) pf/µm2 B. 5 × 10(-4) pf/µm2 C. 8 …
VLSI Design Rule MCQ Quiz – Objective Question with Answer for VLSI Design Rule Read More »
1. Which provides large capacitance? A. load capacitance B. bus wiring capacitance C. sheet capacitance D. area capacitance 2. Bus wiring capacitance is driven through A. one transistor B. two transistors C. three transistors D. no transistors 3. What is the delay of input pads? A. 5Ʈ B. 10Ʈ C. 40Ʈ D. 30Ʈ …
Signal Delay in VLSI MCQ Quiz – Objective Question with Answer for Signal Delay in VLSI Read More »
1. Which provides large capacitance? A. load capacitance B. bus wiring capacitance C. sheet capacitance D. area capacitance 2. Bus wiring capacitance is driven through A. one transistor B. two transistors C. three transistors D. no transistors 3. What is the delay of input pads? A. 5Ʈ B. 10Ʈ C. 40Ʈ D. 30Ʈ …
System Delay MCQ Quiz – Objective Question with Answer for System Delay in VLSI Read More »
1. A 4-bit processor has two buses which are A. unidirectional B. bidirectional C. one unidirectional and one bidirectional D. more than two buses 2. The IN and OUT bus lines relative positions are interchanged to A. match height B. match length C. match width D. match thickness 3. The IN and OUT …
1. Reduction in power dissipation can be brought by A. increasing transistor area B. decreasing transistor area C. increasing transistor feature size D. decreasing transistor feature size 2. When does the longest delay occur in 8:1 inverters? A. during 1 to 0 transition B. during 0 to 1 transition C. during faster speed D. …
1. Which clock is preferred in storage devices? A. single-phase overlapping clock signal B. single-phase non-overlapping clock signal C. two-phase overlapping clock signal D. two-phase non-overlapping clock signal 2. Clock signal Φ2 is to A. write data B. read data C. refresh data D. store data 3. Bits of data may be read …
1. Flash memory is a non-volatile storage device in which data A. can be erased physically B. can be erased magnetically C. can be erased electrically D. cannot be erased 2. NOR-type flash allows ______ to be read or written independently. A. one machine cycle B. one machine word C. one machine sentence D. …
Flash memory MCQ Quiz – Objective Question with Answer for Flash memory Read More »
1. Which method is used to determine structural defects? A. deterministic test pattern B. algorithmic test pattern C. random test pattern D. exhaustive test pattern 2. Which is known as the stored test pattern method? A. deterministic test pattern B. algorithmic test pattern C. random test pattern D. exhaustive test pattern 3. Which …
Memory Cells MCQ Quiz – Objective Question with Answer for Memory Cells Read More »
