VLSI Basic Circuit Concept MCQ Quiz – Objective Question with Answer for VLSI Basic Circuit Concept

101. The capacitance that exists between Gate and Bulk is called ___________

A. Oxide parasitic capacitance
B. Metal oxide capacitance
C. MOS capacitance
D. None of the mentioned

Answer: A

The capacitance that exists between Gate and Bulk is called as an oxide parasitic capacitance.

102. In Cut-off Mode, the capacitance Cgs will be equal to ___________

A. 2Cgd
B. 0
C. Cgb
D. All of the mentioned

Answer: B

In cut-off mode, the conducting channel does not exist, so gate-to-source and the gate-to-drain capacitances are both equal to zero.

103. In cut-off mode, the value of gate to substrate capacitance is equal to ___________

A. Cox .(W- L)
B. Cox W/ L
C. Cox× W×L
D. 0

Answer: C

In Cut-off mode, the conducting channel does not exist, so gate-to-source and the gate-to-drain capacitances are both equal to zero. Therefore, the gate to substrate capacitance is equal to Cox× W×L.

104. In linear mode operation, the parasitic capacitances that exists are ___________

A. Nonzero Gate to source capacitance
B. Nonzero Gate to drain capacitance
C. Zero gate to substrate capacitance
D. All of the mentioned

Answer: D

In linear-mode operation, the conducting channel exists, therefore there will be a finite amount of gate to source and gate to drain capacitances. Since the conducting channel exists, the gate to substrate capacitance is reduced to zero.

105. In saturation mode operation, gate to drain capacitance is zero due to ___________

A. Gate and drain are interconnected
B. Channel length is reduced
C. Inversion layer doesn’t exist
D. Drain is connected to ground

Answer: B

Due to the pinched off-channel, the capacitance between source to drain is reduced to zero.

106. When MOSFET is operating in the saturation region, the gate to source capacitance is?

A. 1/2×Cox×W×L
B. 2/3×Cox×W×L
C. Cox×W×L
D. 1/3×Cox×W×L

Answer: B

Due to the reduction in channel length, the gate to drain, and gate to substrate capacitance are zero, and the gate to channel capacitance as seen between the gate and the source is approximately defined as 2/3×Cox×W×L.

107. The load capacitance is measured between _____

A. Output node and input node
B. Output node and Vcc
C. Output node and ground
D. Input node and ground

Answer: C

The load capacitance is measured at the output node and ground.

108. The load capacitance is equivalent to ___________

A. Sum of all lumped linear capacitances between input and output node
B. Sum of all junction capacitance between Vcc and ground
C. Sum of all junction capacitance between input and output
D. Sum of all lumped linear capacitances between output node and ground

Answer: A

The load capacitance is measured by the sum of all lumped linear capacitances between the input and output nodes.

109. Interconnect capacitance contributes to the load capacitance when the CMOS inverters are connected in a cascade configuration.

A. True
B. False

Answer: A

In cascade configuration, the load capacitance is measured by the sum of all the lumped capacitances and interconnect capacitance.

110. Interconnect capacitance is formed due to ___________

A. Junction capacitance between gate and substrate
B. Wire connecting the gates of 2 different inverters
C. Parasitic capacitance existing between metal and polysilicon connection between 2 inverters
D. All of the mentioned

Answer: C

Parasitic capacitance existing between metal and polysilicon connection between 2 inverters causes the interconnect capacitance.

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