21. The refreshing clock period should propagate through
A. memory cell
B. wiring
C. carry chain
D. any subunit
Answer: B
Clock 2 which is the refreshing clock should propagate through wiring and finite rise and fall time must be allowed.
22. The value of Ʈ for 5-micron technology is always constant.
A. true
B. false
Answer: B
The range of value of Ʈ for 5-micron technology was calculated to be 0.1 to 0.3 nsec but it may vary upto 0.6 nsec.
23. The total clock period for the adder process is
A. 100 nsec
B. 150 nsec
C. 200 nsec
D. 250 nsec
Answer: D
The total clock period of the adder process is 250 nsec which is the sum of all the delays (220 nseC. and the period of different phases of the process.
24. The Zp.u./Zp.d. ratio for the nMOS inverter is
A. 4:1
B. 3:1
C. 1:4
D. 1:3
Answer: A
For nMOS inverters, the Zp.u./Zp.d. ratio is 4:1 when driven from another inverter and 8:1 when driven through one or more pass transistors.
25. The impedance ratio for pseudo-nMOS is
A. 4:1
B. 3:1
C. 1:4
D. 1:3
Answer: B
For pseudo-nMOS, the Zp.u./Zp.d. ratio is 3:1 and for CMOS 1:1 ratio is required for the minimum area.
26. What is the value of peripheral capacitance for 5-micron technology?
A. 4 × 10(-4) pf/µm2
B. 5 × 10(-4) pf/µm2
C. 8 × 10(-4) pf/µm2
D. 12 × 10(-4) pf/µm2
Answer: C
Peripheral capacitance is the sidewall capacitance. The peripheral capacitance of 5-micron technology is 8 × 10(-4) pf/µm2.
27. 1 square Cg is ___________ of MOS transistor.
A. gate to source capacitance
B. gate to drain capacitance
C. source to drain capacitance
D. gate to channel capacitance
Answer: D
1 square Cg is defined as the gate-to-channel capacitance of a MOS transistor having a standard feature size (W=L).
28. What is the delay value Ʈ for 1.2-micron technology?
A. 0.1 nsec
B. 0.12 nsec
C. 0.046 nsec
D. 0.064 nsec
Answer: C
The delay Ʈ is the time constant and for 1.2-micron technology its value is 0.046 nsec.
29. Which is used to increase Ʈ?
A. parasitic capacitance
B. peripheral capacitance
C. area capacitance
D. load capacitance
Answer: A
Circuit wiring and parasitic capacitance must be allowed to increase the value of Ʈ by the factor of 2 or 3.
30. The inverter pair delay is given by
A. (Zp.u./Zp.d.)Ʈ
B. (1+ Zp.u./Zp.d.)Ʈ
C. (1+ Zp.u./Zp.d.)Ʈ
D. (1+ Ʈ)Zp.u./Zp.d.
Answer: B
The inverter delay is given by (1+ Zp.u./Zp.d.)Ʈ. The inverter pair delay for CMOS is 7Ʈ.
